1. Field of the Invention
The present invention relates to a vector data control apparatus, more particularly to an apparatus dealing with vector data having a list structure.
2. Description of the Prior Art
To realize a system for high speed processing of a great amount of data, such as in scientific or technical calculations, it is not sufficient to merely combine typical and conventional general purpose arithmetic units (general purpose computers). To overcome this problem, there has been proposed the concept of a "vector instruction", i.e., an instruction which can process a great amount of data through a single instruction.
Arithmetic units which execute vector instructions are basically operated under the so-called pipeline processing method. The pipeline processing method is a well known method in which sequential data are continuously supplied, one by one, into a plurality of arithmetic stages connected in series with each other, whereby respective resultant data are obtained, one by one, continuously. A vector instruction initiates vector processing. Vector processing in a computer is usually achieved by means of, at least, a plurality of vector registers, a main memory, a plurality of arithmetic units, and means for controlling the operation of the vector registers. The present invention primarily relates to such means.
In the prior art, vector processing is achieved by reading and writing operand data from and to the main memory at a very high speed using a so-called interleave method. In current vector processing, use of the interleave method has no adverse effects on the vector processing since current vector processing is achieved with the use of successive vector data supplied in a regular order. Therefore, the inherent merit of the interleave method, i.e., highly increased thruput of data, can be enjoyed to the fullest along with the usual vector processing.
A problem arises, however, when the vector processing is carried out with the use of vector data supplied not in regular order, but in random order. Such a random order often occurs when the vector data are set up in a so-called list structure. Under such circumstances, there is a likelihood of random specification of the vector data along with the list expression. This necessarily results in random access for the main memory. Accordindly, deleterious bank conflict occurs in the main memory. When such a bank conflict occurs, further, the inherent merit of the interleave method is greatly reduced.